The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, the continuing device miniaturization presents challenges to gap-filling (or trench-filling) dielectric materials. The new generations of devices often have complex topography that needs to be filled by a dielectric material in order to provide a flat top surface for further fabrication processes. The existing gap-filling dielectric materials generally contain multiple molecular components, of which some tend to stay on the top surface of the topography and some tend to stay on the bottom and/or sidewalls of the topography. This causes un-homogenous film property in the resultant dielectric fill layer and may result in delamination of the device and/or other issues.